File: //usr/lib/python3/dist-packages/pygments/lexers/__pycache__/hdl.cpython-38.pyc
U
`a�[ I � @ s� d Z ddlZddlmZmZmZmZmZmZ ddl m
Z
m Z m Z m
Z
mZmZmZmZmZ dddgZG dd� de�ZG d d� de�ZG d
d� de�ZdS ) z�
pygments.lexers.hdl
~~~~~~~~~~~~~~~~~~~
Lexers for hardware descriptor languages.
:copyright: Copyright 2006-2017 by the Pygments team, see AUTHORS.
:license: BSD, see LICENSE for details.
� N)�
RegexLexer�bygroups�include�using�this�words) �Text�Comment�Operator�Keyword�Name�String�Number� Punctuation�Error� VerilogLexer�SystemVerilogLexer� VhdlLexerc @ s� e Zd ZdZdZddgZdgZdgZdZde j
dfd e fd
e fd e fd e j fd
e j
fdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefd efd ejfd ee e j e �fd ee e j e �d fe d!d"d#�e fe d$d%d"d&�e j
fe d'd(d"d&�ej fe d)d"d#�e j fd*ej!fd+efg d,ed-fd.ej"fd/efd efd0efgd1e j
fd2e j
fd3e j d-fd4e j
fd5e j
fd e j
d-fgd6ej d-fgd7�Z#d8d9� Z$d:S );r zZ
For verilog source code with preprocessor directives.
.. versionadded:: 1.4
Zverilog�vz*.vztext/x-verilog�(?:\s|//.*?\n|/[*].*?[*]/)+� ^\s*`define�macro�\n�\s+�\\\n� /(\\\n)?/(\n|(.|\n)*?[^\\]\n)� /(\\\n)?[*](.|\n)*?[*](\\\n)?/�[{}#@]�L?"�string�4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'�%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?� (\d+\.\d*|\.\d+|\d+[fF])[fF]?�([0-9]+)|(\'h)[0-9a-fA-F]+�([0-9]+)|(\'b)[01]+�([0-9]+)|(\'d)[0-9]+�([0-9]+)|(\'o)[0-7]+�\'[01xz]�\d+[Ll]?�\*/�[~!%^&*+=|?:<>/-]�
[()\[\],.;\']�
`[a-zA-Z_]\w*�^(\s*)(package)(\s+)�^(\s*)(import)(\s+)�import)q�always� always_comb� always_ff� always_latch�and�assign� automatic�begin�break�buf�bufif0�bufif1�case�casex�casez�cmos�const�continue�deassign�default�defparam�disable�do�edge�else�end�endcase� endfunction� endgenerate� endmodule�
endpackage� endprimitive�
endspecify�endtable�endtask�enum�event�final�for�force�forever�fork�function�generate�genvar�highz0�highz1�if�initial�inout�input�integer�join�large�
localparam� macromodule�medium�module�nand�negedge�nmos�nor�not�notif0�notif1�or�output�packed� parameter�pmos�posedge� primitive�pull0�pull1�pulldown�pullup�rcmos�ref�release�repeat�return�rnmos�rpmos�rtran�rtranif0�rtranif1�scalared�signed�small�specify� specparamZstrengthr �strong0�strong1�struct�table�task�tran�tranif0�tranif1�type�typedef�unsigned�var�vectored�void�wait�weak0�weak1�while�xnor�xor�\b��suffix)Z
accelerateZautoexpand_vectornetsZ
celldefineZdefault_nettyperH �elsifZ
endcelldefineZendifZ
endprotectZ endprotectedZexpand_vectornetsZifdefZifndefr Z noaccelerateZnoexpand_vectornetsZnoremove_gatenamesZnoremove_netnamesZnounconnected_driveZprotect� protectedZremove_gatenamesZremove_netnamesZresetallZ timescaleZunconnected_driveZundef�`)�prefixr� )4�bitsZ
bitstorealZbitstoshortrealZ countdriversZdisplayZfcloseZfdisplayZfinishZfloorZfmonitorZfopenZfstrobeZfwriteZ
getpattern�historyZincsaverb Zitor�key�list�logZmonitorZ
monitoroffZ monitoronZnokeyZnologZprinttimescaleZrandomZreadmembZreadmemh�realtimeZ
realtobits�resetZ reset_countZ reset_valueZrestartZrtoiZsaveZscaleZscopeZshortrealtobitsZ
showscopesZ
showvariablesZshowvarsZ sreadmembZ sreadmemhZstime�stopZstrobe�timeZ
timeformat�writez\$��byte�shortint�int�longintrc r� �bit�logic�reg�supply0�supply1�tri�triand�trior�tri0�tri1�trireg�uwire�wire�wandZ woshortreal�realr� �[a-zA-Z_]\w*:(?!:)�\$?[a-zA-Z_]\w*�"�#pop�/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})� [^\\"\n]+�\\�[^/\n]+�/[*](.|\n)*?[*]/�//.*?\n�/� (?<=\\)\n� [\w:]+\*?)�rootr r r/ c c s> t �| |�D ],\}}}|tkr,|�� r,tj}|||fV q d S �N�r �get_tokens_unprocessedr �isupper�Constant��self�text�index�token�value� r� �5/usr/lib/python3/dist-packages/pygments/lexers/hdl.pyr� � s
� z#VerilogLexer.get_tokens_unprocessedN)%�__name__�
__module__� __qualname__�__doc__�name�aliases� filenames� mimetypes�_wsr �Preprocr �Single� Multiliner r
�Charr �Float�Hex�Bin�Integer�Octr r
r r� r r � Namespacer �Builtin�Type�Label�Escape�tokensr� r� r� r� r� r s�
��� ��
�
� ���O�
�
��cc @ s� e Zd ZdZdZddgZddgZdgZdZde j
d fd
e e e
je �fd e e e
je �d fd
e fde fde fde jfde jfdefdedfdejfdejfdejfdejfdejfdejfdejfd efd ejfd efd efd efd!e j fe d"d#d$�e
fe d%d#d$�e j
fe d&d#d$�e j fd'e e
e �d(fe d)d#d$�e
j fd*e j!fd+e fg d,e j"d-fgd.ed-fd/ej#fd0efdefd1efgd2e j
fd3e jfd4e jd-fd5e j
fd6e j
fd
e j
d-fgd7e jd-fgd8�Z$d9d:� Z%d;S )<r z�
Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
1800-2009 standard.
.. versionadded:: 1.5
Z
systemverilogZsvz*.svz*.svhztext/x-systemverilogr r r r- r. r/ r r r r r r r r r r! r" r# r$ r% r& r' r( r) r* r+ r, )�Z accept_on�aliasr0 r1 r2 r3 r4 �assertr5 Zassumer6 Zbeforer7 ZbindZbinsZbinsofr� r8 r9 r: r; r� r< r= r> ZcellZchandleZchecker�classZclockingr? Zconfigr@ Z
constraint�contextrA ZcoverZ
covergroupZ
coverpointZcrossrB rC rD ZdesignrE ZdistrF rG rH rI rJ Z
endcheckerZendclassZ endclockingZ endconfigrK rL ZendgroupZ endinterfacerM rN rO Z
endprogramZ endpropertyZ endsequencerP rQ rR rS rT Z
eventuallyZexpectZexportZextendsZexternrU Z first_matchrV rW ZforeachrX rY ZforkjoinrZ r[ r\ �globalr] r^ r_ ZiffZifnoneZ ignore_binsZ illegal_binsZimpliesr/ Zincdirr r` ra rb Zinside�instancer� rc Z interfaceZ intersectrd Zjoin_anyZ join_nonere ZletZliblist�libraryZlocalrf r� r� rg Zmatchesrh Zmodportri rj rk �newZnexttimerl rm Znoshowcancelledrn ro rp �nullrq rr �packagers rt ru rv rw ZpriorityZprogram�propertyr� rx ry rz r{ Zpulsestyle_ondetectZpulsestyle_onevent�pureZrandZrandcZrandcaseZ randsequencer| r� r� r} r� Z reject_onr~ r Zrestrictr� r� r� r� r� r� Zs_alwaysZ s_eventuallyZ
s_nexttimeZs_untilZ s_until_withr� Zsequencer� Z shortrealZ
showcancelledr� r� Zsolver� r� Zstaticr Zstrongr� r� r� �superr� r� Zsync_accept_onZsync_reject_onr� Ztaggedr� r Z
throughoutr� Z
timeprecisionZtimeunitr� r� r� r� r� r� r� r� r� r� r� �union�uniqueZunique0r� �untilZ
until_withZuntyped�user� r� r� Zvirtualr� r� Z
wait_orderr� Zweakr� r� r� Zwildcardr� �withZwithinZworr� r� r� r� )z `__FILE__z `__LINE__z`begin_keywordsz `celldefinez`default_nettypez`definez`elsez`elsifz
`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz `resetallz
`timescalez`unconnected_drivez`undefz `undefineall)Lz$displayz $displaybz $displayhz $displayoz$dumpallz $dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz
$dumpportsallz$dumpportsflushz$dumpportslimitz
$dumpportsoffz $dumpportsonz $dumpvarsz$fclosez $fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz$finishz $fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez $fstrobebz $fstrobehz $fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$monitorz $monitorbz $monitorhz $monitoroz $monitoroffz
$monitoronz $plusargsz$randomz $readmembz $readmemhz$rewindz$sformatz $sformatfz$sscanfz$strobez$strobebz$strobehz$strobeoz$swritez$swritebz$swritehz$swriteoz$testz$ungetcz$value$plusargsz$writez$writebz$writehz
$writemembz
$writememhz$writeoz (class)(\s+)� classnamer� r� r� z [a-zA-Z_]\w*r� r� r� r� r� r� r� r� r� r� r� )r� r r r r/ c c s> t �| |�D ],\}}}|tkr,|�� r,tj}|||fV q d S r� r� r� r� r� r� r� s
� z)SystemVerilogLexer.get_tokens_unprocessedN)&r� r� r� r� r� r� r� r� r� r r� r r r r� r� r� r r
r� r r� r� r� r� r� r r
r r� r r� r� r� �Classr� r� r� r� r� r� r� r � s�
�!�#�������a
��
�
��xc @ s� e Zd ZdZdZdgZddgZdgZej ej
B Z de fde fde fd e
jfd
ejfd efd ejfd
efdefdeee ej�fdeee e�fdeee eje�fdeee ej�fdeejej�feddd�ejfdeee ej�fdeee eje ee eje e� fdeejee e�fdeee�e �dfe d �e d �e d �d efge d �d ejfd e fd!ed"fged#dd�ej fged$dd�efgd%e j fd&e j fd'e j fd(e j!fd)e j"fd*e j#fgd+�Z$d,S )-r z:
For VHDL source code.
.. versionadded:: 1.5
Zvhdlz*.vhdlz*.vhdz text/x-vhdlr r r z--.*?$z'(U|X|0|1|Z|W|L|H|-)'r* z
'[a-z_]\w*r+ z "[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z (use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))ZstdZieeeZworkr� r� z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)�endblock�types�keywords�numbersz [a-z_]\w*z(\s+)�;r� )Zbooleanr� � characterZseverity_levelrc r� Z delay_lengthZnaturalZpositiver Z
bit_vectorZfile_open_kindZfile_open_statusZ
std_ulogicZstd_ulogic_vectorZ std_logicZstd_logic_vectorr� r� )_�abs�accessZafterr� �allr4 Z architectureZarrayr� Z attributer7 �blockZbody�bufferZbusr< Z componentZ
configurationZconstantZ
disconnectZdowntorH r� rI Zentity�exit�filerV rZ r[ Zgeneric�groupZguardedr_ Zimpure�inZinertialra �isZlabelr� Zlinkage�literalZloop�map�modrj r� �nextrm rn r� ZofZon�openrq Zothers�outr ZportZ postponedZ procedureZprocessr �range�record�registerZrejectZremr� ZrolZrorZselectZseverity�signalZsharedZslaZsllZsraZsrlZsubtypeZthen�toZ transportr� Zunitsr r Zvariabler� Zwhenr� r r� r� z\d{1,2}#[0-9a-f_]+#?z\d+z (\d+\.\d*|\.\d+|\d+)E[+-]?\d+z
X"[0-9a-f_]+"z
O"[0-7_]+"z B"[01_]+")r� r r r
r N)%r� r� r� r� r� r� r� r� �re� MULTILINE�
IGNORECASE�flagsr r r� r
r� r
r Z Attributer r r r� r r
r r r r� r r� r� r� r� r� r� r� r� r� r� r ! s� �� � �
� � ����'���� �����)r� r& Zpygments.lexerr r r r r r Zpygments.tokenr r r
r r r
r r r �__all__r r r r� r� r� r� �<module> s
,
{